Yet more changes to the stellaris logic analyser (here, here and here). This version returns to using the internal RAM buffer but sampling is now SysTick interrupt driven.
This allows the sample rate to be variable so that a lower sample rate can be used to gain a longer capture time. Sample rates up to 2MHz seem usable, anything above that gave me incorrectly detected baud rates in ols's UART analyser.
Updated firmware, binary file and OLS-Profile: sllogiclogger.2013-02-10.tar.gz.
Sample rates have been changed to more closely match bus pirate's; code has been pushed to github.
Another modification to the stellaris logic analyser (here and here) code, this time removing the RAM buffer altogether and writing the data out to the UART immediately. The advantage of removing it that we can then do continuous capture - well we could if ols v0.9.6.1 supported it, so instead we capture 1MB as that's the most it'll will deal with. The downside is that the sample rate is limited by the speed of the UART and even with it set to 460800bps the sample rate is only 45.605kHz - at this rate we can capture 8 channels for 22.99 seconds.
To keep the capture loop as tight as possible it will continue to capture/send data even after ols has finished, to capture again you'll need to reset the stellaris. Don't forget to set the port speed to 460800bps in ols.
Reading though the docs - it looks like it might be possible to use DMA between the PORT and the UART on the stellaris to increase the sample rate; I'm also working on RLE encoding to pack more into the RAM buffer used on the previous code.
Updated firmware, binary file and OLS-Profile: sllogiclogger.2013-02-09.tar.gz.
This is a trivial modification to Fischl.de's TI Stellaris Launchpad logic analyser. I've simply increased the buffer length from 16KB to 31KB increasing the capture length from 1.64ms to 3.17ms.
Updated firmware, binary file and OLS-Profile: sllogiclogger.2013-02-03.tar.gz